1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, it relates to a semiconductor memory device including SRAM (static random access memory) cells.
2. Description of the Background Art
A semiconductor memory device employing a single-port SRAM cell having a single port for inputting/outputting data is known in general. FIG. 15 is a circuit diagram showing an exemplary conventional single-port SRAM cell 206. Referring to FIG. 15, the exemplary conventional single-port SRAM cell 206 is constituted of six transistors in total, i.e., four n-channel transistors NT201, NT202, NT206 and NT207 and two p-channel transistors PT201 and PT202.
In operation, a semiconductor memory device employing the exemplary conventional single-port SRAM cell 206 shown in FIG. 15 holds the potential of a word line WL at a low level in an initial state. Thus, the semiconductor memory device holds the potentials of the gates of the n-channel transistors NT201 and NT202 at low levels, thereby holding the n-channel transistors NT201 and NT202 in OFF states. When the potentials of nodes ND201 and ND202 are at high and low levels respectively in this state, the potentials of the gates of the n-channel transistor NT207 and the p-channel transistor PT202 go high, thereby turning the n-channel transistor NT207 and the p-channel transistor PT202 on and off respectively. At this time, the n-channel transistor NT202 is in the OFF state, and hence a ground potential is supplied through the n-channel transistor NT207 for holding the potential of the node ND202 at the low level.
The potentials of the gates of the n-channel transistor NT206 and the p-channel transistor PT201 go low due to the potential of the node ND202 held at the low level, thereby turning the n-channel transistor NT206 and the p-channel transistor PT201 off and on respectively. At this time, the n-channel transistor NT201 is in the OFF state, and hence a positive voltage Vcc is supplied through the p-channel transistor PT201 for holding the node ND201 at the high level.
In the single-port SRAM cell 206, as hereinabove described, it is possible to hold the potentials of the nodes ND201 and ND202 by holding the n-channel transistors NT201 and NT202 in the OFF states. When a high-level signal for selecting a row address is supplied to the word line WL, the potentials of the gates of the n-channel transistors NT201 and NT202 rise to high levels, thereby turning on the n-channel transistors NT201 and NT202. Thus, data can be written in/read from the single-port SRAM cell 206 through a pair of bit lines BL and /BL.
When the semiconductor memory device employing the exemplary conventional single-port SRAM cell 206 shown in FIG. 15 selects a prescribed word line WL and supplies a high-level signal thereto, however, the n-channel transistors NT201 and NT202 of all single-port SRAM cells 206 connected to this word line WL are turned on. Thus, all pairs of bit lines BL and /BL connected to all single-port SRAM cells 206 connected to the word line WL supplied with the high-level signal are activated. Therefore, a prescribed SRAM cell 206 cannot be accessed through a second system while the same is accessed through a first system. Thus, the access from the second system enters the wait state during the access from the first system, and hence it is disadvantageously difficult to improve the operating speed in the semiconductor memory device employing the exemplary conventional single-port SRAM cell 206 shown in FIG. 15.
In order to solve the problem of the semiconductor memory device employing the exemplary conventional single-port SRAM cell 206 shown in FIG. 15, there are proposed various types of semiconductor memory devices improving operating speeds by employing dual-port SRAM cells allowing simultaneous data writing and data reading from two different systems. For example, Japanese Patent Laying-Open No. 5-109279 (1993) proposes such a semiconductor memory device.
FIG. 16 is a circuit diagram showing a conventional dual-port SRAM cell 209 disclosed in Japanese Patent Laying-Open No. 5-109279. Referring to FIG. 16, the conventional dual-port SRAM cell 209 is constituted of eight transistors in total, i.e., six n-channel transistors NT203, NT204 and NT208 to NT211 and two p-channel transistors PT203 and PT204. This dual-port SRAM cell 209 comprises two ports for inputting/outputting data, dissimilarly to the exemplary conventional single-port SRAM cell 206 shown in FIG. 15. The two ports are constituted of the n-channel transistors NT203 and NT204 and the n-channel transistors NT210 and NT211 respectively. A pair of bit lines BL1 and /BL1 and a word line WL1 are connected to the port constituted of the n-channel transistors NT203 and NT204. Further, another pair of bit lines BL2 and /BL2 and another word line WL2 are connected to the port constituted of the n-channel transistors NT210 and NT211. The n-channel transistors NT208 and NT209 and the p-channel transistors PT203 and PT204 are similar in circuit structure to the n-channel transistors NT206 and NT207 and the p-channel transistors PT201 and PT202 shown in FIG. 15 respectively.
In operation of a semiconductor memory device employing the conventional dual-port SRAM cell 209 shown in FIG. 16, the n-channel transistors NT208 and NT209 and the p-channel transistors PT203 and PT204 hold the potentials of nodes ND203 and ND204 similarly to those in the semiconductor memory device employing the single-port SRAM cell 206 shown in FIG. 15. When a high-level signal for selecting a row address is supplied to the word line WL1, the potentials of the gates of the n-channel transistors NT203 and NT204 rise to high levels, thereby turning on the n-channel transistors NT203 and NT204. Thus, data can be written in/read from the dual-port SRAM cell 209 through the pair of bit lines BL1 and /BL1. When the high-level signal for selecting the row address is supplied to the word line WL2, on the other hand, the potentials of the gates of the n-channel transistors NT210 and NT211 rise to high levels, thereby turning on the n-channel transistors NT210 and NT211. Thus, data can be written in/read from the dual-port SRAM cell 209 through the pair of bit lines BL2 and /BL2. In this case, the pair of bit lines BL2 and /BL2 are not activated when the high-level signal is supplied to the word line WL1 while the pair of bit lines BL1 and /BL1 are not activated when the high-level signal is supplied to the word line WL2, whereby a second dual-port SRAM cell 209 can be accessed through a second port while a first dual-port SRAM cell 209 is accessed through a first port. Thus, the semiconductor memory device employing the dual-port SRAM cell 209 can simultaneously write/read data in/from two different dual-port SRAM cells 209 from two different systems of the pairs of bit lines BL1 and /BL1 and BL2 and /BL2, whereby the semiconductor memory device can be simultaneously accessed through two different systems. Thus, access from a second system can be inhibited from entering the wait state during access from a first system, whereby the operating speed of the semiconductor memory device can be improved.
However, the conventional dual-port SRAM cell 209 shown in FIG. 16 must be provided with the two pairs of bit lines BL1, /BL1, BL2 and /BL2 and the two word lines WL1 and WL2 in correspondence to the two ports provided on the dual-port SRAM cell 209, and hence the numbers of the bit lines BL1, /BL1, BL2 and /BL2 and the word lines WL1 and WL2 are disadvantageously doubled as compared with the single-port SRAM cell 206. Thus, the space for arranging the bit lines BL1, /BL1, BL2 and /BL2 and the word lines WL1 and WL2 is disadvantageously increased. In the dual-port SRAM cell 209 constituted of the eight transistors, i.e., the n-channel transistors NT203, NT204 and NT208 to NT211 and the p-channel transistors PT203 and PT204, further, the number of the transistors is disadvantageously increased as compared with the single-port SRAM cell 206 constituted of the six transistors. Thus, the cell area of the dual-port SRAM cell 209 is disadvantageously increased as compared with the single-port SRAM cell 206 due to the increased number of the transistors. Therefore, the space for arranging the bit lines BL1, /BL1, BL2 and /BL2 and the word lines WL1 and WL2 as well as the cell area are increased in the conventional dual-port SRAM cell 209 shown in FIG. 16, to disadvantageously increase the size of the semiconductor memory device. Thus, the size of the semiconductor memory device constituted of only dual-port SRAM cells must disadvantageously be increased in order to improve the operating speed thereof.